In general, a PDP is thin, has no flicker and possesses a large display contrast ratio. Further, it can be made into a relatively large screen, has a fast response speed, and is self-luminous. It is capable of emitting light of multiple colors by utilizing fluorescent material. Since PDPs have numerous good characteristics, they have been widely used in the fields of computer-related display devices and color image display in recent years.
FIG. 8 is a block diagram showing an example of a conventional driver device of a PDP according to a related art. In the PDP, a sustain electrode group 42 and a scanning electrode group 53, which are parallel to each other, are provided on one side, and a data electrode group 32 is provided perpendicular to the other electrode groups on the opposing plane. Display cells 22 are formed at the intersections of these groups. The sustain electrodes X correspond to and are provided adjacent to each of the scanning electrodes Y1, Y2, Y3, . . . , Yn (where n is a positive integer) and they are connected in common to each other at one end.
Next, the structures of several kinds of driver circuits for driving the display cells 22 and a control circuit for controlling these driver circuits are described. A data driver 31 that drives data for one line of the data electrode group 32 in order to produce an address discharge in the display cells 22, a sustain electrode driver circuit 40 that causes a common sustain discharge to the sustain electrode group 42 in order to produce a sustain discharge in the display cells 22, and a scanning electrode driver circuit 50 that causes a common sustain discharge to the scanning electrode group 53 are provided. Furthermore, a scanning driver 55 is provided to sequentially scan the scanning electrodes Y1 to Yn of the scanning electrode group 53 in order to produce a selective write discharge in an addressing discharge period. The scanning driver 55 produces a sustain discharge by applying a sustain pulse sent from the scanning electrode driver circuit 50 to its own power supply. A control circuit unit 61 controls every operation of the data driver 31, the sustain electrode driver circuit 40, the scanning electrode driver circuit 50, the scanning driver 55, and a PDP 21. The main part of the control circuit unit 61 comprises a display data control unit 62 and a driving timing control unit 63. The display data control unit 62 has functions of rearranging externally received display data so as to drive the PDP 21, and temporarily storing the rearranged display data row so as to transfer the rearranged data as display data DATA to the data driver 31 at the time of a sequential scanning by the scanning driver 55 at an addressing discharge. The driving timing control unit 63 converts various signals externally received (such as a dot clocks) to internal control signals for driving the PDP 21 and respectively controls each driver and driver circuits.
Here, an address driver circuit that concerns the present invention will be described in detail. The data driver 31 shown in FIG. 8 is generally composed of a plurality of PDP data driver ICs having tens to hundreds of display data output terminals.
The PDP data driver IC (hereinafter “data driver IC”) has the function of outputting a data pulse corresponding to display data to a PDP panel. The data driver IC generally has tens to hundreds of terminals for outputting data pulses, which can be either at a high or low level. The data driver IC is composed of a shift register 101, a latch circuit 102, an output control circuit 103, and a level shifter+high breakdown voltage buffer 104 as shown in FIG. 9.
The shift register 101 has the function of transferring display data 106 received from one or multiple display data input terminal(s) using a CLK 105 and storing it. Further, the latch circuit 102 has the function of capturing the display data stored in the shift register 101 into the register via a latch input terminal 107. The display data captured by the latch circuit 102 is outputted from an output terminal 108 as a data pulse signal via the output control circuit 103 and the level shifter+high breakdown voltage buffer 104. The output control circuit 103 generally comprises a control terminal 109 for setting all data pulse outputs of the data driver IC to a high level and a control terminal 110 for setting all the outputs to a low level. Furthermore, the level shifter+high breakdown voltage buffer 104 includes a level shifter for converting the signal level of the output control circuit 103 and supplying it to the output stage.
In recent years, the number of display cells for PDPs has increased greatly as multi-gradation display has become more common and the screens have become larger. The number of lighting cells to be written and the value of the peak current that flows through the scanning electrodes during write discharge have also increased, causing the voltage drop due to the impedances of the electrodes and driver circuit to be large. In order to prevent this and perform a stable write discharge, scanning pulses and data pulses of a higher voltage must be applied. However, this might increase the power consumption of the device.
As a method for reducing power consumption associated with driving a PDP, power recovery (electric charge recovery) is known (refer to Patent Document 1). In this method, electric charges generated during the light emission of the PDP are collected while it is not emitting light and reused at the next light emission. In this case, the electric charges accumulated in the display cells are collected via the output stage of the aforementioned level shifter+high breakdown voltage buffer.
As the output stage of a high breakdown voltage buffer, one constituted by a CMOS circuit and one constituted by a totem-pole circuit where two NchMOS transistors are cascade-connected are known. For instance, the one constituted by a CMOS circuit is disclosed in Patent Document 1, and those constituted by a totem-pole circuit are disclosed in Patent Documents 2 and 3. When power is recovered, electric charges accumulated in display cells are collected through the transistor on the high potential side of the output stage in either circuit structure.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-51648A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2004-310108A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-11-68540